Despite weaker smartphone sales and mounting geopolitical risks, TSMC remains unfazed. Chairman and CEO C.C. Wei reaffirmed ...

TSMC is on track to qualify its ultra-large version of chip-on-wafer-on-substrate (CoWoS) packaging technology that will offer an interposer size of up to nine reticle sizes and 12 HBM4 memory ...

When Amkor announced plans to build a $1.6 billion chip test and packaging facility near Peoria, Arizona, it was clear that the company planned to serve TSMC’s customers in the state. Apple is ...

TSMC’s CoWoS packaging triples capacity by 2025, enhancing AI chip efficiency and capturing high-margin revenue. While competitors struggle, TSMC is accelerating to 2nm production, securing its ...

Intel has marked the official launch of its contract chip manufacturing business to compete against Asian foundry giants TSMC and Samsung ... update to its process road map.

The priority at this site is to ramp up production of TSMC’s SoIC (System on Integrated Chip) technology. At the company’s AP8 facility, which mainly focuses on expanding CoWoS ...

This test chip was implemented using TSMC's cutting-edge N3P process technology and CoWoS-R advanced packaging technology. The HBM4 IP supports data rates of up to 12 Gbps under all operating ...

The complete PHY and Controller subsystem was developed in collaboration with TSMC and targets applications such as hyperscaler, high-performance computing (HPC) and artificial intelligence (AI).

Hsinchu, Taiwan – June 8, 2021 – Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced today that it has successfully taped out AI/HPC/Networking CoWoS® Platform with 7.2 Gbps HBM3 ...